In my journey with VHDL projects, I’ve recognized the importance of maintaining a clear and organized folder structure, even for personal endeavors. Without a systematic approach, projects can quickly become chaotic. It’s all too easy to find simulation files entangled with synthesis files, or to lose track amidst a sea of IP core libraries. As projects grow, effective version control becomes an uphill battle, and the challenges multiply.
To combat these issues and streamline my workflow, I’ve developed an automated system tailored for VHDL-based FPGA projects. Think of it as a nod to the initialization process of npm projects, albeit simpler and more focused. Currently, my go-to for testing is ModelSIM, but I’m eyeing a transition to vUnit in the near future. For now, let me share my template for an organized FPGA project structure.
<ProjectName>
│
├── docs # Documentation and notes
│
├── hdl # All your HDL source files (VHDL, Verilog)
│ ├── src # Main source files
│ └── tb # Testbenches
│
├── ipcores # IP cores (either generated by Vivado or third-party)
│ ├── src # Main IP core source files
│ └── tb # IP core testbenches
│
├── constraints # Constraint files (.xdc for Vivado)
│
├── scripts # Automation scripts, Tcl scripts for Vivado, etc.
│
├── sim # Simulation-related files
│ ├── modelsim # ModelSim-specific files
│ │ ├── work # ModelSim compiled libraries
│ │ └── wave # Saved waveforms, if any
│ └── logs # Simulation logs
│
├── synthesis # Synthesis output files
│ ├── vivado # Vivado-specific files
│ │ ├── runs # Synthesis and implementation runs
│ │ ├── logs # Logs from Vivado runs
│ │ └── checkpoints # Checkpoints for various stages
│ └── reports # Synthesis and implementation reports
│
└── output # Final output files (bitstreams, binaries, etc.)
I also prepared a python script to create this folder tree with a zero effort. Feel free to use it. If you have any suggestion to update it do not hesitate to reach me out!
Happy coding!
