In VHDL, a wrapper is a module that serves as an interface between two different design entities. It typically has two main functions: to adapt the interface of one entity to the interface of another, and to provide a boundary between the two entities to isolate them from each other.
Here is an example of a wrapper in VHDL:
In this example, the wrapper module is called “wrapper” and it has a generic parameter called “DATA_WIDTH” that determines the width of the data inputs and outputs. It also has two ports: “clk” and “rst” which are used for clock and reset signals, and “in_data” and “out_data” which are the input and output data signals.
Inside the wrapper, there is a component called “design_entity_A” which represents the other design entity that the wrapper is interfacing with. The wrapper has the same interface as “design_entity_A”, but it also has an additional intermediate data signal called “intermediate_data” which is used to buffer the output of “design_entity_A” before it is passed to the output of the wrapper.
The wrapper instantiates “design_entity_A” and maps its generic and port parameters to the corresponding values in the wrapper. It then uses a process to synchronize the output of “design_entity_A” to the output of the wrapper using the clock signal “clk” and the reset signal “rst”.
